Dynamic random access memories (DRAMS) are used extensively in electronic circuits, especially in circuits requiring great amounts of memory in a very rapid computing environment. The personal computer is likely the greatest market for these circuits, but other markets also exist, from telecommunications, to Internet and electronic-commerce applications, to graphics and publishing. Whatever the application, users and manufacturers constantly seek to improve both computers and their memories, looking for improvements in everything from software to hardware to better interactions between the two.
One area for improvement is increasing reliability in manufacturing. An important goal is to catch errors and stop production as soon as possible after a manufacturing error is made. If DRAMS are manufactured with faults, then not only are the parts and DRAMS lost, but all the time, effort and investment that went into processing those parts are also lost. Such mistakes may be caught by in-process checks. In-process checks are not an ideal solution, because such checks tend to catch mistakes after they are made, rather than preventing mistakes or improving the process that made the mistakes. However, in-process checks may be necessary for certain types of manufacturing, especially if the processes are not amenable to reliability improvements. Assemblies may benefit from in-process checks if the individual parts from which the assemblies are made cannot be reliably checked individually.
This will be particularly true for defects of such a nature that they do not completely prevent a portion of a memory device from functioning, but rather slow the device down. Thus, a defect which breaks a path in a word line or a bit line, an open in the circuit, can be detected because it will disable a portion of the device, at least that word line or bit line. Defects may also occur that will slow down the memory device, such as a thin portion in the polysilicon or the cladding layer typically formed above the polysilicon. Such a defect will not disable the particular word line or bit line in which it occurs, but may slow down the device or portion of the device by a few nanoseconds. Such a slowing may or may not be evident on a less-than-100% functional check given DRAMS in production testing, but may become evident when the DRAM is put into service.
Checking every bit in a memory device will not detect this sort of defect, nor will functional tests, such as a “butterfly” test, in which a single bit is written to and the surrounding bits are also written to. The single bit is then checked, and the device or the memory is assessed. By repeating this test in several ways, i.e., vertically, horizontally, and diagonally, defects or subsets of problems within devices may be detected. There are other tests and patterns that may be used, but these tests tend to detect relatively direct problems, rather than more subtle problems that only manifest themselves when a particular type of program or particular portion of the memory or the device is used.
DRAMS may be considered as assemblies of many parts, and in particular, they may be thought of as assemblies of the individual DRAM memory devices or modules. When the devices are assembled, the address lines for the devices may be a single address line connected to all the devices. This may also apply to command lines. By lines are meant the traces or circuits on the silicon by which signals are sent from one location to another.
The test environment for a single device is very different from the test environment for a number of devices assembled into a DRAM module. Tests, especially functional and timing tests for the addresses on the devices, may yield significantly different results from tests of individual devices. This difference may be caused by the much smaller capacitance of an address line or a command line connected to one device as compared to the capacitance of an address line or a command line connected to a multitude of devices.
What is needed is a way to make a test environment as realistic as possible for an individual memory device as for the assembled DRAM module. What is needed is a way to simulate in testing the conditions and capacitance seen by an individual DRAM memory device as it would be in an assembled DRAM module.